Technological innovations in semiconductor fabrication technologies are driving market demands for semiconductor memory devices providing higher storage capacity, higher speed, higher integration density, and lower power consumption. The downscaling of semiconductor memory devices to submicron design rules and beyond, however, coupled with increased storage capacity poses technological challenges with respect to maintaining performance and reliability. For instance, as memory capacity increases and the pitch between adjacent patterns are made narrower, the layout of the memory arrays and peripheral devices become more problematic, especially with regard to memory core layout. When designing memory circuits, it is desirable to minimize the length and loading of word lines. Indeed, if word lines are too long/narrow and/or have too many memory cells connected to each word line (i.e., a large load), word line enable driver circuits will consume more power to drive the word lines, and the speed of driving word lines can decrease. To mitigate the impact on device performance with line rule downscaling and increased memory density, various memory circuit architectures have been employed including, for example, hierarchical memory bank architectures and hierarchical word line driver structures with sub word line architectures.
For instance, FIGS. 1A˜1C are schematic illustrations of a semiconductor memory device having a conventional hierarchical memory bank architectures and hierarchical word line driver framework. FIG. 1A illustrates a semiconductor integrated circuit memory chip (10) having a memory cell array with a memory capacity of 1 Gb, which is divided into a plurality of memory banks, Bank A, B, C and D (or more generally, Bank-i) (e.g., 4 memory banks of 256 Mb). Each memory bank Bank-i can be independently operated with associated peripheral circuits including column decoders (11) and row decoders (12), as well as other I/O circuitry for outputting/inputting data via peripheral data I/O pads (13). Each memory bank Bank-i comprises decoder circuits and core circuits that are arranged in “unit blocks,” as depicted in FIG. 1B. In particular, FIG. 1B schematically illustrates a conventional layout of each memory bank (Bank_i) in FIG. 1A, wherein each memory bank (Bank-i) comprises a plurality of 256 unit blocks BL(i) including 16 unit blocks along an x-direction (bitline/column direction) and 16 unit blocks along a y-direction (word line/row direction).
FIG. 1C schematically illustrates a conventional layout pattern for each unit block BL-i in the memory bank Bank-i for a memory device utilizing a hierarchical sub-word line driver scheme. Each unit block BL-i includes a cell array (20), sub-word line driver (SWD) arrays (21), bit line sense amplifier (BSLA) arrays (23) and conjunction circuit blocks including PXiD driver blocks (22) and LA driver (LADRV) blocks (24). The unit block pattern BL-i depicted in FIG. 1C is repeated in both x and y directions over the memory bank Bank-i such that each memory cell array block (20) is disposed between two BLSA blocks (23) in the x (column) direction of bit lines and such that each memory cell array block (20) is disposed between two sub-word line drivers (21) in the y (word line) direction. In one conventional hierarchical word line framework, each block sense amplifier (23) is shared by two memory cell array blocks (20) to the left and right of the BLSA (23) and each sub-word line driver (21) is shared by two memory cell array blocks (20) above and below the SWD block (21) using an interleaved layout framework, as is known in the art.
By way of specific example, FIG. 2 is a schematic illustration of one conventional framework of a unit block BL-i such as depicted in FIG. 1C in a semiconductor device having a hierarchical divided word line scheme. As shown in FIG. 2, a memory cell array (20) includes an array of memory cells MC (each having a cell transistor and cell capacitor in a DRAM memory) located at the intersection of a bit line BL or BLB and a sub-word line WL. The bit lines are connected to the memory cells MC and to corresponding sense amplifiers SA in BLSA blocks (23) using an open bitline architecture, for example, as is known in the art. The BSLA blocks (23) are driven by control signals generated by drivers in respective LADRV blocks (24). In the hierarchical divided word line scheme, a word line is divided into a plurality of sub-word lines WL that are driven using corresponding sub-word line driver blocks (21) located above and below the memory cell array (20).
FIGS. 3, 4 and 5 are schematic diagrams to illustrate a conventional I/O architecture of for a multi-bank semiconductor memory device. In general, FIG. 3 is a schematic block diagram illustrating I/O circuitry for data read/write data paths for a conventional DRAM core comprising a plurality of banks. FIG. 4 schematically illustrates a layout arrangement of local and global data I/O bus lines providing a core data path from the memory cells and global bus lines for a multi-bank semiconductor device. FIG. 5 schematically illustrates a layout of the I/O circuitry and bus lines within the memory cell array regions and in peripheral regions of the memory arrays. FIGS. 3, 4, and 5 illustrate a typical device having an open bit line structure where bit lines BL and inverted bit lines BLB extend to both sides of a sense amplifier (23i) and where memory cells (MC) are formed at intersection region of the bit lines and word lines. Bit line pairs BL, BLB are respectively placed at both sides of each sense amplifier (23i) in a given array.
As shown in FIG. 3, each sense amplifier (23i) is shared by two memory cell arrays and is connected to local data lines LIO and /LIO by pass gates M1, M2 which are gated by the column select line CSL. As explained below, each column select line (CSL) may control multiple sense amplifiers per sense amplifier array, where each sense amplifier serves one data line pair. An LGIO multiplexer circuit (30) connects local data I/O line pairs LIO, /LIO to global data I/O line pairs GIO, /GIO. A GIO multiplexer circuit (31) connects the global data I/O line pars GIO, /GIO to data I/O line pairs DIO, /DIO at the input to a data read path and at the output of a data write path. The data read path includes IO sense amplifiers (32), a data bus multiplexer (33) and data output buffer (34) to output data to the appropriate output pads 13 upon memory read access operations. The data write path receives data input via the pads (13) at a data input buffer (35), a multiplexer circuit (36) and a data driver (37) to drive respective DIO line pairs.
To read out one or a plurality of data from the memory cells of the semiconductor memory device, the data stored in the cells are amplified in the bitline sense amplifier (23i). The data amplified in the bitline sense amplifier (23i) are transferred to the local data I/O lines LIO and /LIO) via a column selection line (CSL) switch, amplified in an LIO sense amplifier connected to the LIO bus, and then transferred to the global I/O buss. Data read from a selected memory block is transmitted to data line pairs DIO, /DIO via the GIO multiplexer (31). Data line sense amplifiers (32) sense data transferred via the data lines DIO and /DIO. The data line multiplexer (33) selects from among the output signals of the data line sense amplifiers (32), and transmits the selected output data signals to pads (13) via the data output buffer (34).
FIG. 4 schematically illustrates a layout structure of data lines from a memory cell to global I/O lines. As shown in FIG. 4, the semiconductor memory device includes alternating odd and even numbered memory cell blocks (101, 102, 103) with array of sense amplifiers interposed between the arrays. The LIO bus lines include two pairs (110) and (111) local I/O lines LIO, LIOB that extends over the sense amplifiers (i.e., parallel to the word lines) between the arrays and service the bit line sense amplifiers located within an array. The global I/O lines extend parallel to the bit lines over the full length of the memory array. The LIO bus lines may be formed from a first metallization level whereas the GIO bus lines are formed using a second metallization level. In the exemplary embodiment of FIG. 4, each CSL (column select line) is connected to the column switch circuit for 2 sense amplifiers on each side of the cell arrays and one CSL signal output form a column decoder (13) will activate the two pairs of sense amplifiers on each side of the cell arrays. This allows for DDR (dual data rate) memory access operations where 4 sets of LIO data can be transferred to the GIO lines for each CSL activation.
FIG. 5A illustrates an exemplary layout of the I/O circuitry and bus lines. As shown, the GIO bus lines extends over the entire memory bank towards a peripheral regions between the column decoders (130) of adjacent memory banks. The peripheral regions includes the GIO multiplexer circuit (31), the I/O sense amplifier circuit (32) and the DB multiplexer circuitry. Moreover, data I/O bus lines DIOB extend over substantially the entire length of the peripheral region between the top and bottom side of the memory banks and then extend across the top regions of the memory banks towards DOUT buffers and the DQ pads disposed at the peripheral edge regions of the semiconductor memory chip. Due to long lengths, repeater circuit (40) may be included along the DOIB bus lines. The repeaters (40) operate to buffer and transmit data on the DOIB lines between data pad and the DB multiplexer circuit (33) and thereby reduces the load and decreases the delay of the data signals of the DOIB lines.
When current sensing is used on the data lines, the transmission distances from the memory blocks to the data line sense amplifier vary. Accordingly, current from a memory block close to the data line sense amplifier travels a shorter length of the data lines and experiences less resistance on the data lines between the memory block and the data lines sense amplifier. Current from a memory block far away from the data line sense amplifier experiences more resistance on the data lines between that memory block and the data lines sense amplifier. Accordingly, the data line sense amplifier often has different sensing efficiency for different memory blocks. For instance, as shown in FIG. 5B, memory access operation to the upper left side of the memory bank (e.g., BANK A) must travel a long path along the GIO lines toward the column decoder (13) for the bank, and then up and down the FDIO and DOIB bus lines in the peripheral regions and then back towards the output pads over the top side of the memory bank A from between the column decoders (130). This can lead to differences in access times for read operations, which is particularly undesirable for a memory device such as a synchronous DRAM (SDRAM) where timing of data signals is critical. The problem becomes more significant for larger capacity memories because the relative differences in transmission lengths typically increase with an increase in the memory capacity and the integration density. Accordingly, a need exists for a semiconductor memory device capable of keeping the sensing efficiency of a data line sense amplifier uniform.